Computer Organization & Architecture: Module 1 Essentials

This cheat sheet covers the fundamental concepts of computer organization and architecture, including functional units, memory concepts, processor architectures (CISC/RISC), and assembly language programming.

Core Principles

• Computers have five functional units: Input, Output, Memory, ALU, and Control Unit.
• Endianness defines byte order in memory (Big-Endian vs. Little-Endian).
• A memory map details address allocation for hardware components.
• CISC uses complex, variable-length instructions; RISC uses simple, fixed-length instructions.
• Assembler directives guide the assembly process without generating machine code.
• The instruction execution cycle involves Fetch, Decode, Execute, Write Back, and Interrupt Check.
• The stored program concept allows data and instructions to share the same memory.
• Von Neumann architecture is the foundation of modern computers.
• Pipelining overlaps instruction phases to increase throughput.
• Pipeline hazards (structural, data, control) can stall execution.

Key Terms

• Functional Units: Input, Output, Memory, ALU, Control Unit.
• Endianness: Byte order in memory (Big-Endian: MSB first; Little-Endian: LSB first).
• Memory Map: Diagram showing memory address allocation.
• CISC: Complex Instruction Set Computer; many complex, variable-length instructions.
• RISC: Reduced Instruction Set Computer; simple, fixed-length instructions.
• Assembler Directives: Commands to the assembler (e.g., .data, .text).
• Instruction Execution Cycle: Fetch-Decode-Execute cycle.
• Stored Program Concept: Data and instructions share the same memory.
• Pipelining: Overlapping instruction execution stages.
• Pipeline Hazard: Situation preventing normal pipeline execution (structural, data, control).

Real World Examples

• Storing a multi-byte number (0x12345678): Big-Endian: 12|34|56|78; Little-Endian: 78|56|34|12.
• Processor Architectures: CISC: Intel x86; RISC: MIPS, ARM.
• Instruction Execution: Pipelining allows multiple instructions to be in different stages of execution simultaneously.

Timeline

• 1975: IBM 801 project by John Cocke - first RISC-like processor.
• 1981: RISC-I at UC Berkeley by David Patterson.
• 1981: MIPS at Stanford by John Hennessy - pipelined RISC design.
• 1987: MIPS R2000/R3000 - commercial RISC success.
• Post-1980s: ARM, SPARC, PowerPC emerge as dominant RISC processors.

People

• John Cocke: Pioneered RISC architecture with IBM 801 project.
• David Patterson: Led RISC-I development at UC Berkeley.
• John Hennessy: Developed pipelined RISC design at Stanford (MIPS).
• William Stallings: Author of the reference textbook.