Computer Organization & Architecture: Module 1 Essentials

This cheat sheet covers fundamental concepts of computer organization, including functional units, memory addressing (endianness), memory maps, and the distinction between CISC and RISC architectures. It also touches on assembly language directives and instruction execution.

Core Principles

Five functional units: Input, Output, Memory, ALU, Control Unit.
Endianness: Byte order in memory (Big-Endian vs. Little-Endian).
Memory Map: Allocates addresses to hardware components.
CISC: Complex instructions, variable length, many addressing modes.
RISC: Simple instructions, fixed length, load/store architecture.
Assembler directives guide assembly without generating machine code.

Action Steps

Identify the five core functional units of a computer.
Distinguish between Big-Endian and Little-Endian byte ordering.
Understand how a memory map defines address allocation.
Compare and contrast CISC and RISC architectures.
Recognize the role of assembler directives in program development.

Key Terms

Functional Units: Input, Output, Memory, ALU, Control Unit – the core components of a computer.
Endianness: The byte order used to store multi-byte data in memory.
Big-Endian: Most significant byte (MSB) at the lowest memory address.
Little-Endian: Least significant byte (LSB) at the lowest memory address.
Memory Map: Diagram/table showing memory address allocation to hardware components.
CISC: Complex Instruction Set Computer; large, complex instructions.
RISC: Reduced Instruction Set Computer; small, simple instructions.
Assembler Directive: Command to the assembler, guiding the assembly process (e.g., .data, .text).
Instruction Execution Cycle: Fetch-Decode-Execute cycle for processing instructions.
Stored Program Concept: Data and instructions share the same memory (Von Neumann architecture).

Timeline

Early 1980s: RISC architecture research begins at IBM, Stanford, and UC Berkeley.
1975: IBM 801 project by John Cocke – first RISC-like processor.
1981: RISC-I at UC Berkeley (David Patterson) – 31 instructions, large register file.
1981: MIPS at Stanford (John Hennessy) – pipelined RISC design.
1987: MIPS R2000/R3000 – commercial RISC success.

People

John Cocke: Pioneer of RISC architecture (IBM 801 project).
David Patterson: Key researcher in RISC architecture (UC Berkeley, RISC-I).
John Hennessy: Key researcher in RISC architecture (Stanford, MIPS).