RTL to GDS II Design Flow

This cheat sheet outlines the standard RTL to GDS II flow for ASIC design, detailing key steps from high-level design to the final manufacturing layout.

Core Principles

RTL (Register Transfer Level) is a behavioral description of a digital circuit.
GDS II is a standard file format for IC layout data.
The flow transforms an abstract design into a physical layout.
Each step involves synthesis, optimization, and verification.
Tool choices (like Cadence) significantly impact efficiency and results.

Action Steps

1. RTL Design: Write Verilog/VHDL code describing circuit functionality.
2. Synthesis: Convert RTL to a gate-level netlist using standard cells.
3. Floorplanning: Define chip area, power grid, and placement of major blocks.
4. Placement: Position standard cells within the floorplan.
5. Clock Tree Synthesis (CTS): Create a balanced clock distribution network.
6. Routing: Connect placed cells according to the netlist.
7. Timing Closure: Optimize placement and routing to meet timing constraints.
8. Physical Verification (DRC/LVS): Ensure layout adheres to manufacturing rules and matches the schematic.
9. GDS II Generation: Output the final layout in GDS II format for fabrication.

Key Terms

RTL: Register Transfer Level: A description of a digital circuit's behavior using registers and logic operations.
GDS II: Graphic Design System II: A standard file format for semiconductor manufacturing data.
Synthesis: Process of converting RTL code into a gate-level netlist.
Netlist: A description of the components and their interconnections in a circuit.
Standard Cells: Basic building blocks (gates, flip-flops) in a technology library.
Floorplanning: Initial chip layout stage defining overall dimensions and macro placement.
CTS: Clock Tree Synthesis: Building the network to distribute the clock signal.
DRC: Design Rule Check: Verifies layout against manufacturing constraints.
LVS: Layout Versus Schematic: Ensures the layout matches the intended circuit design.

Pro Tips

Use linting tools early to catch RTL errors.
Create a detailed timing budget for each block.
Consider power and signal integrity from the start.
Iterate between timing closure and physical verification.
Automate repetitive tasks with scripting.

Pitfalls to Avoid

Ignoring setup/hold time violations.
Poor floorplanning leading to routing congestion.
Inadequate clock tree balancing causing skew.
Over-reliance on automated tools without understanding.
Insufficient verification at each stage.

Real World Examples

Designing a CPU core.: RTL describes the instruction set logic; GDS II is the final chip blueprint.
Implementing a memory controller.: Synthesis creates the gate-level logic; placement and routing connect these gates physically.
Developing a graphics processing unit (GPU).: The entire RTL to GDS II flow is critical for complex chip architectures.

Timeline

Early Stage: RTL Design & Functional Verification
Synthesis: RTL to Gate-Level Netlist Conversion
Physical Design Start: Floorplanning & Initial Placement
Mid Physical Design: Placement, CTS, Routing
Timing Closure: Optimization for Performance
Verification Sign-off: DRC, LVS, Extraction
Final Output: GDS II Generation

People

Cadence Design Systems: Provider of EDA tools used in the RTL to GDS II flow (e.g., Genus, Innovus).